PCB Design Manual

Quick Checklist

• Schematic is complete and accurate
• Units and grids set
• All components placed on the board
• Functional blocks identified
• Critical tracks routed first
• Power and ground routed
• Design Rule Check (DRC) passed
• Silkscreen and solder mask checked
• Manufacturing rules checked
• Design reviewed by someone else

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1. Before You Start

Schematic

• Must be complete and accurate. No “circuit in my head” or loose notes.
• Draw signals flowing left-to-right: inputs on the left, outputs on the right.
• Add layout notes, e.g. “guard track to signal ground”.
• Draw the schematic with the PCB layout in mind.

Units

• Use imperial for layout: thou = 1/1000 inch.
  • 1 thou = 1 mil. Avoid saying “mil” if it can be confused with millimetre.
• 100 thou = 2.54 mm
  
• 200 thou = 5.08 mm
  
• 0.1 inch pitch = 100 thou
  
• 1.27 mm = 50 thou
• Use metric for mechanical/manufacturing: hole sizes, board dimensions.
• Learn the unit-toggle hotkey in your CAD package (e.g. Q in Protel).

Grids

• Use a snap grid.
• 100 thou: basic through-hole placement.
• 50 thou: general tracking.
• 25 thou: fine routing, halfway between 50 thou pads.
• Finer grids: 20, 10, 5 thou. Must be an even division of 100 thou.
• Visible grid: often 100 thou.
• Electrical grid: snaps cursor to pad/track centres.
• Component grid: multiple of the snap grid.

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2. Component Placement

Rule: PCB design is 90% placement and 10% routing.

Placement Procedure

1. Set snap grid, visible grid, and default track/pad sizes.
2. Place all components on the board.
3. Divide the circuit into functional “building blocks”.
4. Identify critical tracks.
5. Route critical tracks first.
6. Place and route each block separately, off-board.
7. Move completed blocks into position.
8. Route remaining signal and power connections.
9. Tidy up the board.
10. Run DRC.
11. Get someone to check it.

Placement Rules

• Neatly line up ICs, resistors, capacitors, and connectors.
• Symmetry is good, but electrical performance comes first.
• Separate:
  • Digital and analog
  • High-frequency and low-frequency
  • High-current and low-current
• Use the rats nest display to guide placement.
• Do not space components evenly just for looks; use space efficiently.
• Put connectors on the edge of the board where practical.

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3. Routing

• Keep nets as short as possible.
• Use 45° angles only. No right angles, no angles >90°.
• “Snake” tracks around the board; avoid point-to-point routing.
• Enable electrical grid / snap-to-centre.
• Always route to the centre of the pad.
• Use a single track, not multiple tracks tacked end-to-end.
• Only take one track between 100 thou pads unless absolutely necessary.
• Neck down between pads when required.
• Route power and ground first if critical. Make power tracks as wide as possible.
• Keep power and ground tracks close together.
• Use multiple vias for high-current layer changes.
• Do not leave unconnected copper fills (“dead copper”). Ground them or remove them.
• Do not drag tracks to non-45° angles.
• On non-plated through boards, do not place vias under components.

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4. Tracks, Pads, Vias, Polygons

Track Width

• Bigger is better: lower resistance, lower inductance, easier to etch and inspect.
• Typical starting points:
  • 25 thou signal
  • 50 thou power/ground
  • 10–15 thou between IC/component pads
• Manufacturer track/space figure: e.g. 10/8 means min track 10 thou, min space 8 thou.
• Typical: 10/10 or 8/8. IPC lower limit: 4 thou.
• Necking: wide → narrow → wide.
• Copper thickness: 1 oz standard. Also available: 0.5 oz, 2 oz, 4 oz.

Pads

• Pad/hole ratio: pad ≥ 1.8 × hole diameter, or ≥ 0.5 mm larger.
• Leaded components: round pads, ~70 thou diameter.
• DIL ICs: oval pads, ~60 thou high × 90–100 thou wide.
• Pin 1: rectangular pad, same dimensions as other pins.
• SMD: rectangular pads. SO packages: oval pads. Pin 1 rectangular.
• Avoid octagonal pads.

Vias

• Plated Through Holes (PTH) connect layers.
• Via hole typical: 0.5–0.7 mm.
• Do not use pads as vias, or vias as pads.
• Stitching: using vias to connect layers.
• Minimise vias; each via adds two solder joints.

Polygons

• Place polygons after tracks and pads.
• Solid fills preferred; hatched fills are obsolete.
• Useful for ground planes.

Clearances

• Basic through-hole: ≥ 15 thou.
• Dense SMD: 10 or 8 thou.
• 240 V mains: minimum 8 mm (315 thou) between mains and isolated signal tracks.
• Use IPC tables for other voltages (see Appendix B).

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5. Layers

Silkscreen

• Component outlines, designators (C1, R1, etc.), and text.
• Keep text size and orientation consistent.
• Mark polarised components and pin 1.
• Do not rely on silkscreen for positional accuracy.
• No silkscreen overlap with bare pads.
• Do not put component values on silkscreen—just designators.

Solder Mask

• Polymer coating around pads to prevent solder bridging.
• Essential for SMD and fine-pitch devices.
• Mask expansion: usually a few thou.
• Standard colour: green.
• SMOBC (Solder Mask Over Bare Copper) is standard.
• Tenting: covering vias with solder mask.

Mechanical Layer

• Board outline and manufacturing instructions.

Keepout

• Areas where routing is not allowed.

Layer Alignment

• Allow tolerances for artwork, drilling, and layer alignment.

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6. Netlists, Rats Nest, DRC

• Netlist: list of connections from the schematic.
• Rats nest: straight lines showing connectivity before routing.
• DRC: checks connectivity, clearance, and manufacturing tolerances.
• Forward annotation: schematic → PCB.
• Back annotation: PCB → schematic.

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7. Power, Grounding, Bypassing

Power Planes

• Dedicate layers to ground and power on multilayer boards.
• Ground plane is first preference.
• Keep power planes away from board edges.
• Use split planes to separate analog and digital grounds.
• Use multiple vias to lower impedance.

Good Grounding

• Use lots of copper.
• Use star grounding for critical parts.
• Run separate ground paths back to the main filter capacitor.
• Stitch points directly to the ground plane.
• Use multiple vias to reduce trace impedance to ground.

Good Bypassing

• One bypass capacitor per IC or switching component.
• Typical values:
  • 100 nF general purpose
  • 10 nF or 1 nF for higher frequencies
  • 1 µF or 10 µF for low frequencies
• Place bypass capacitors as close as possible to the power pin.
• Never replace multiple bypass capacitors with one.
• Use low-ESR capacitors for critical designs.

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8. High-Frequency Design

• A track becomes a transmission line if it is too long.
• Signal travels roughly 6 inches per nanosecond on FR4.
• Critical length: when track length approaches half of that.
• Use a ground plane for controlled impedance.
• Microstrip: trace on top layer, ground plane below.
• Stripline: trace between two ground planes.
• Keep high-frequency tracks as short as possible.
• Avoid ground-plane cutouts under high-frequency tracks.
• One decoupling capacitor per power pin.
• Track the IC power pin to the bypass capacitor first, then to the power plane.
• Minimise crosstalk:
  • Minimise distance between trace and plane.
  • Maximise distance between traces.
• Smaller vias have lower parasitic inductance.

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9. Finishing Touches

• Chamfer T-junctions on thin tracks (<25 thou).
• Check mounting holes are clear of components and tracks.
• Minimise the number of different hole sizes.
• Check hole sizes for all components.
• Make all vias identical where possible.
• Check physical spacing between components.
• Use draft mode to spot sloppy tracks and off-centre pads.
• Add teardrops automatically if your CAD package supports it.

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10. Design for Manufacturing

Panelisation

• Put multiple boards on one panel to reduce assembly cost.
• Tooling strips on top and bottom.
• Use breakout tabs or V-grooves.

Tooling Strips

• Blank board with tooling holes and fiducials.
• Standard hole sizes: 2.4 mm, 3.2 mm.
• Four tooling holes per panel, one per corner.

Fiducial Marks

• Visual alignment for pick-and-place machines.
• 3 global fiducials on the panel.
• 1.5 mm circular pad, solder mask clearance ≥ 3 mm.
• Local fiducials next to fine-pitch SMD devices.

Thermal Relief

• Prevents heat sinking when soldering pads connected to large copper areas.
• Usually 4 smaller tracks connecting pad to plane.

Soldering

• Hand soldering: allow access for iron, use thermal relief.
• Wave soldering: solder mask essential; watch for shadowing.
• Reflow soldering: solder paste stencil, oven.
• Mixed through-hole and SMD: wave + reflow.

Surface Finishes

• Tin: low-cost.
• SMOBC + HAL: standard professional finish.
• Gold flash: for fine-pitch SMD.
• Peelable solder mask: temporary masking.

Electrical Testing

• Flying probe or bed-of-nails.
• Mandatory for multilayer boards.

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11. Submitting for Manufacture

Checklist

• Reference code and revision
• Turnaround time
• Quantity
• Board thickness (1.6 mm standard)
• Material (FR4 standard)
• Number of layers
• Surface finish (SMOBC + HAL standard)
• Solder mask and overlay colour
• Copper weight (1 oz standard)
• Electrical testing
• Track/space clearance
• Board dimensions definition (e.g. mechanical layer)
• Panelised or individual boards

File Format

• Protel format is common in Australia.
• Gerber is universal but can introduce errors if generated incorrectly.
• Supply the original PCB package file if possible.

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Appendix A: Track Width Reference (10°C Rise)

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Appendix B: Clearance for Electrical Conductors

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Appendix C: FR4 Properties

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Rules of Thumb

• 100 thou = 2.54 mm
• 50 thou = 1.27 mm
• 1 oz copper ≈ 1.4 thou thick
• Signal speed on FR4 ≈ 6 in/ns
• 10°C temperature rise is a safe track limit
• Pad ≥ 1.8 × hole diameter
• 15 thou clearance basic; 8–10 thou for dense boards
• 8 mm clearance for 240 V mains
• One bypass capacitor per IC
• 45° angles only

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Final Note

Good PCB design takes experience. Start with placement, keep it neat, follow the rules, and always review your work.

Happy routing!

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